The present invention relates to a phase-locked loop (to be referred to as a PLL hereinafter) and, more particularly, to a PLL with improved input jitter characteristics.
FIG. 1 is a block diagram showing a conventional PLL. In FIG. 1, reference numeral 1 denotes a phase comparator; 2, a voltage-controlled oscillator; and 3, a low-pass filter.
In the conventional PLL of this arrangement, an input signal S1 is compared with an output signal S4 of the voltage-controlled oscillator 2 by the phase comparator 1. An output signal S2 as a comparison result of these signals is input to the low-pass filter 3, and the voltage-controlled oscillator 2 is controlled by an output signal S3 filtered through the filter 3.
In the arrangement of the conventional PLL, a jitter pass band (noise band width) is narrowed as much as possible to maintain good output jitter characteristics.
In the conventional PLL, however, a hysteresis exists in the synchronization characteristics of the PLL with respect to an input low-frequency jitter amount characteristic to FM modulation. Therefore input jitter characteristics are degraded. In other words, since hysteresis is present with respect to a change in frequency shift amount in the low-frequency modulation range of the FM modulation, input jitter characteristics are degraded.